The Present Situation, Challenges and Development of CMOS 3D Stacking Technology

Abstract

CMOS 3D stacking technology, as a key path to breaking through the bottleneck of Moore's Law, solves the physical limitation and interconnect delay issues faced by traditional two-dimensional scaling through expansion in the vertical dimension. This article systematically reviews the latest progress of this technology in the three pivotal trends of interconnects, thermal management, and architecture design. In terms of interconnect technology, the emphasis is on bumpless hybrid bonding, which is a process of achieving sub-micron high-density vertical interconnects reliably through the simultaneous bonding of Cu-Cu and SiO₂. In terms of thermal management, this article involves modeling optimization based on equivalent thermal conductivity and embedded microchannel cooling technologies, displaying a paradigm shift from passive conduction to active fluid-based heat radiation. At the architectural level, the paper analyzes strategies for the co-optimization of heterogeneous integration and Electronic Design Automation (EDA), especially the potential of software-defined near-memory computing architectures to break the “memory wall”. Research indicates that the paradox problem between heat and electricity in high-density integration can be effectively solved thanks to the innovation across the "material-process-architecture" nexus, paving the way for a theoretical reference for process route selection in next-generation high-performance chips.